URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] [vhdl/] - Rev 40

Rev	Log message	Author	Age	Path
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7399d 22h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
38	add measures to implement XCHD	arniml	7402d 02h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
37	add dump_compare support	arniml	7402d 02h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
32	rename pX_limp to pX_low_imp	arniml	7407d 20h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
29	take auxiliary carry from direct ALU connection	arniml	7408d 18h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
28	update wiring for DA support	arniml	7408d 18h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
27	implemented mnemonic DA	arniml	7408d 19h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
26	support for DA instruction	arniml	7408d 19h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
24	connect control signal for Port 2 expander	arniml	7409d 03h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
23	rework Port 2 expander handling	arniml	7409d 03h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7409d 03h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7409d 03h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
20	move code for PROG out of if-branch for xtal3_s	arniml	7409d 03h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
7	initial check-in	arniml	7412d 18h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
6	moved to system directory	arniml	7412d 18h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/
4	initial check-in	arniml	7413d 18h	/t48/tags/rel_0_6_1_beta/rtl/vhdl/