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[/] [t48/] [tags/] [rel_0_6_1_beta/] [rtl/] [vhdl/] - Rev 44

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Rev Log message Author Age Path
44 default assignment for aux_carry_o arniml 7424d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
43 fix sensitivity list arniml 7425d 11h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7425d 13h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
38 add measures to implement XCHD arniml 7427d 17h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
37 add dump_compare support arniml 7427d 17h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
32 rename pX_limp to pX_low_imp arniml 7433d 12h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
29 take auxiliary carry from direct ALU connection arniml 7434d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
28 update wiring for DA support arniml 7434d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
27 implemented mnemonic DA arniml 7434d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
26 support for DA instruction arniml 7434d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
24 connect control signal for Port 2 expander arniml 7434d 18h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
23 rework Port 2 expander handling arniml 7434d 18h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7434d 18h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A		 arniml 7434d 18h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
20 move code for PROG out of if-branch for xtal3_s arniml 7434d 18h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
7 initial check-in arniml 7438d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
6 moved to system directory arniml 7438d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/
4 initial check-in arniml 7439d 10h /t48/tags/rel_0_6_1_beta/rtl/vhdl/

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