URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [sw/] [i8039emu/] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5594d 17h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
256	This commit was manufactured by cvs2svn to create tag 'rel_0_6_1_beta'.		6565d 02h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7304d 15h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
124	fix wrong handling of MB after return from interrupt	arniml	7305d 12h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
123	support hex file for external ROM	arniml	7305d 12h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
88	allow memory bank switching during interrupts	arniml	7368d 10h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
74	enhance pass/fail detection	arniml	7375d 15h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
58	add periodic interrupt	arniml	7384d 05h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7385d 06h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7385d 06h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/
49	Imported sources	arniml	7390d 08h	/t48/tags/rel_0_6_1_beta/sw/i8039emu/