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[/] [t48/] [tags/] [rel_0_6__beta/] - Rev 257

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Rev	Log message	Author	Age	Path
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6599d 19h	/t48/tags/rel_0_6__beta/
193	iManual	arniml	6870d 12h	/t48/tags/rel_0_6__beta/
192	update list for Wishbone toplevel	arniml	6870d 23h	/t48/tags/rel_0_6__beta/
191	preliminary version 0.2	arniml	6871d 03h	/t48/tags/rel_0_6__beta/
190	finalize change log for release 0.6 beta	arniml	6871d 21h	/t48/tags/rel_0_6__beta/
189	add bug report "Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"	arniml	6902d 23h	/t48/tags/rel_0_6__beta/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6902d 23h	/t48/tags/rel_0_6__beta/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6903d 00h	/t48/tags/rel_0_6__beta/
186	update to version 0.2	arniml	6904d 01h	/t48/tags/rel_0_6__beta/
185	initial check-in	arniml	6908d 23h	/t48/tags/rel_0_6__beta/
184	initial check-in	arniml	6909d 00h	/t48/tags/rel_0_6__beta/
183	fix missing assignment to outclock	arniml	6909d 03h	/t48/tags/rel_0_6__beta/
182	intermediate version	arniml	6989d 02h	/t48/tags/rel_0_6__beta/
181	fix typo	arniml	6989d 05h	/t48/tags/rel_0_6__beta/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6997d 10h	/t48/tags/rel_0_6__beta/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6997d 10h	/t48/tags/rel_0_6__beta/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6998d 22h	/t48/tags/rel_0_6__beta/
177	Implement db_dir_o glitch-safe	arniml	6998d 22h	/t48/tags/rel_0_6__beta/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6998d 22h	/t48/tags/rel_0_6__beta/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	7000d 01h	/t48/tags/rel_0_6__beta/

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[/] [t48/] [tags/] [rel_0_6__beta/] - Rev 257

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