URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6__beta/] [bench/] - Rev 292

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5570d 19h	/t48/tags/rel_0_6__beta/bench/
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6541d 04h	/t48/tags/rel_0_6__beta/bench/
183	fix missing assignment to outclock	arniml	6850d 11h	/t48/tags/rel_0_6__beta/bench/
160	add others to case statement	arniml	7128d 09h	/t48/tags/rel_0_6__beta/bench/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7167d 09h	/t48/tags/rel_0_6__beta/bench/
133	add checks for PSEN	arniml	7211d 04h	/t48/tags/rel_0_6__beta/bench/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7324d 17h	/t48/tags/rel_0_6__beta/bench/
110	exchange syn_rom for lpm_rom	arniml	7324d 17h	/t48/tags/rel_0_6__beta/bench/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7328d 14h	/t48/tags/rel_0_6__beta/bench/
83	connect if_timing to P2 output of T48	arniml	7350d 08h	/t48/tags/rel_0_6__beta/bench/
82	check expander timings	arniml	7350d 08h	/t48/tags/rel_0_6__beta/bench/
81	initial check-in	arniml	7350d 12h	/t48/tags/rel_0_6__beta/bench/
80	added if_timing	arniml	7350d 12h	/t48/tags/rel_0_6__beta/bench/
68	connect T0 and T1 to P1	arniml	7357d 10h	/t48/tags/rel_0_6__beta/bench/
67	initial check-in	arniml	7357d 10h	/t48/tags/rel_0_6__beta/bench/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7361d 08h	/t48/tags/rel_0_6__beta/bench/
33	rename pX_limp to pX_low_imp	arniml	7377d 09h	/t48/tags/rel_0_6__beta/bench/
30	connect prog_n_o	arniml	7378d 07h	/t48/tags/rel_0_6__beta/bench/
19	enhance simulation result string	arniml	7380d 06h	/t48/tags/rel_0_6__beta/bench/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7382d 05h	/t48/tags/rel_0_6__beta/bench/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6__beta/] [bench/] - Rev 292

Filtering Options