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[/] [t48/] [tags/] [rel_0_6__beta/] [bench/] [vhdl/] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5628d 10h	/t48/tags/rel_0_6__beta/bench/vhdl/
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6598d 19h	/t48/tags/rel_0_6__beta/bench/vhdl/
183	fix missing assignment to outclock	arniml	6908d 02h	/t48/tags/rel_0_6__beta/bench/vhdl/
160	add others to case statement	arniml	7186d 00h	/t48/tags/rel_0_6__beta/bench/vhdl/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7225d 00h	/t48/tags/rel_0_6__beta/bench/vhdl/
133	add checks for PSEN	arniml	7268d 19h	/t48/tags/rel_0_6__beta/bench/vhdl/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7382d 09h	/t48/tags/rel_0_6__beta/bench/vhdl/
110	exchange syn_rom for lpm_rom	arniml	7382d 09h	/t48/tags/rel_0_6__beta/bench/vhdl/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7386d 05h	/t48/tags/rel_0_6__beta/bench/vhdl/
83	connect if_timing to P2 output of T48	arniml	7407d 23h	/t48/tags/rel_0_6__beta/bench/vhdl/
82	check expander timings	arniml	7407d 23h	/t48/tags/rel_0_6__beta/bench/vhdl/
81	initial check-in	arniml	7408d 04h	/t48/tags/rel_0_6__beta/bench/vhdl/
80	added if_timing	arniml	7408d 04h	/t48/tags/rel_0_6__beta/bench/vhdl/
68	connect T0 and T1 to P1	arniml	7415d 01h	/t48/tags/rel_0_6__beta/bench/vhdl/
67	initial check-in	arniml	7415d 01h	/t48/tags/rel_0_6__beta/bench/vhdl/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7418d 23h	/t48/tags/rel_0_6__beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7435d 00h	/t48/tags/rel_0_6__beta/bench/vhdl/
30	connect prog_n_o	arniml	7435d 23h	/t48/tags/rel_0_6__beta/bench/vhdl/
19	enhance simulation result string	arniml	7437d 21h	/t48/tags/rel_0_6__beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7439d 21h	/t48/tags/rel_0_6__beta/bench/vhdl/

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[/] [t48/] [tags/] [rel_0_6__beta/] [bench/] [vhdl/] - Rev 292

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