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[/] [t48/] [tags/] [rel_0_6__beta/] [rtl/] [vhdl/] - Rev 345

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5607d 13h	/t48/tags/rel_0_6__beta/rtl/vhdl/
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6577d 22h	/t48/tags/rel_0_6__beta/rtl/vhdl/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6881d 02h	/t48/tags/rel_0_6__beta/rtl/vhdl/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6881d 02h	/t48/tags/rel_0_6__beta/rtl/vhdl/
183	fix missing assignment to outclock	arniml	6887d 05h	/t48/tags/rel_0_6__beta/rtl/vhdl/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6975d 13h	/t48/tags/rel_0_6__beta/rtl/vhdl/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6975d 13h	/t48/tags/rel_0_6__beta/rtl/vhdl/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6977d 01h	/t48/tags/rel_0_6__beta/rtl/vhdl/
177	Implement db_dir_o glitch-safe	arniml	6977d 01h	/t48/tags/rel_0_6__beta/rtl/vhdl/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6977d 01h	/t48/tags/rel_0_6__beta/rtl/vhdl/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6978d 04h	/t48/tags/rel_0_6__beta/rtl/vhdl/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7007d 00h	/t48/tags/rel_0_6__beta/rtl/vhdl/
171	remove obsolete output stack_high_o	arniml	7008d 00h	/t48/tags/rel_0_6__beta/rtl/vhdl/
169	initial check-in	arniml	7009d 12h	/t48/tags/rel_0_6__beta/rtl/vhdl/
168	change address range of wb_master	arniml	7009d 12h	/t48/tags/rel_0_6__beta/rtl/vhdl/
167	simplify address range: - configuration range - Wishbone range	arniml	7009d 12h	/t48/tags/rel_0_6__beta/rtl/vhdl/
166	assign default for state_s	arniml	7011d 04h	/t48/tags/rel_0_6__beta/rtl/vhdl/
165	add component wb_master.vhd	arniml	7012d 03h	/t48/tags/rel_0_6__beta/rtl/vhdl/
164	initial check-in	arniml	7012d 03h	/t48/tags/rel_0_6__beta/rtl/vhdl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7013d 03h	/t48/tags/rel_0_6__beta/rtl/vhdl/

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[/] [t48/] [tags/] [rel_0_6__beta/] [rtl/] [vhdl/] - Rev 345

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