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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 140

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Rev Log message Author Age Path
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7233d 13h /t48/tags/rel_0_6_beta/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7234d 23h /t48/tags/rel_0_6_beta/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7234d 23h /t48/tags/rel_0_6_beta/
137 add link to COMPILE_LIST arniml 7272d 12h /t48/tags/rel_0_6_beta/
136 initial check-in arniml 7272d 12h /t48/tags/rel_0_6_beta/
135 add bug
PSENn Timing		 arniml 7276d 22h /t48/tags/rel_0_6_beta/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7277d 08h /t48/tags/rel_0_6_beta/
133 add checks for PSEN arniml 7277d 08h /t48/tags/rel_0_6_beta/
132 stop simulation upon assertion error arniml 7277d 08h /t48/tags/rel_0_6_beta/
131 update arniml 7277d 08h /t48/tags/rel_0_6_beta/
130 initial check-in arniml 7277d 08h /t48/tags/rel_0_6_beta/
129 cleanup copyright notice arniml 7339d 16h /t48/tags/rel_0_6_beta/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7346d 19h /t48/tags/rel_0_6_beta/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7346d 20h /t48/tags/rel_0_6_beta/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7346d 21h /t48/tags/rel_0_6_beta/
125 exclude from dump compare arniml 7346d 21h /t48/tags/rel_0_6_beta/
124 fix wrong handling of MB after return from interrupt arniml 7347d 18h /t48/tags/rel_0_6_beta/
123 support hex file for external ROM arniml 7347d 18h /t48/tags/rel_0_6_beta/
122 test MB after return from interrupt arniml 7347d 18h /t48/tags/rel_0_6_beta/
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7350d 11h /t48/tags/rel_0_6_beta/

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