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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 154

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Rev Log message Author Age Path
154 added t8039_notri hierarchy arniml 7158d 14h /t48/tags/rel_0_6_beta/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7159d 12h /t48/tags/rel_0_6_beta/
152 added hierarchy t8048_notri and system components package arniml 7160d 03h /t48/tags/rel_0_6_beta/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7160d 03h /t48/tags/rel_0_6_beta/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7160d 11h /t48/tags/rel_0_6_beta/
149 update arniml 7160d 11h /t48/tags/rel_0_6_beta/
148 initial check-in arniml 7160d 11h /t48/tags/rel_0_6_beta/
147 initial check-in for release 0.5 BETA arniml 7196d 12h /t48/tags/rel_0_6_beta/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7197d 12h /t48/tags/rel_0_6_beta/
145 remove PROG and end of XTAL2, see comment for details arniml 7197d 13h /t48/tags/rel_0_6_beta/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7197d 13h /t48/tags/rel_0_6_beta/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7197d 14h /t48/tags/rel_0_6_beta/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7197d 14h /t48/tags/rel_0_6_beta/
141 disable external memory to avoid conflicts with outl a, bus arniml 7197d 14h /t48/tags/rel_0_6_beta/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7197d 14h /t48/tags/rel_0_6_beta/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7199d 01h /t48/tags/rel_0_6_beta/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7199d 01h /t48/tags/rel_0_6_beta/
137 add link to COMPILE_LIST arniml 7236d 13h /t48/tags/rel_0_6_beta/
136 initial check-in arniml 7236d 13h /t48/tags/rel_0_6_beta/
135 add bug
PSENn Timing		 arniml 7240d 23h /t48/tags/rel_0_6_beta/

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