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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 183

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Rev	Log message	Author	Age	Path
183	fix missing assignment to outclock	arniml	6870d 16h	/t48/tags/rel_0_6_beta/
182	intermediate version	arniml	6950d 15h	/t48/tags/rel_0_6_beta/
181	fix typo	arniml	6950d 18h	/t48/tags/rel_0_6_beta/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6958d 23h	/t48/tags/rel_0_6_beta/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6959d 00h	/t48/tags/rel_0_6_beta/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6960d 11h	/t48/tags/rel_0_6_beta/
177	Implement db_dir_o glitch-safe	arniml	6960d 12h	/t48/tags/rel_0_6_beta/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6960d 12h	/t48/tags/rel_0_6_beta/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6961d 14h	/t48/tags/rel_0_6_beta/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6961d 15h	/t48/tags/rel_0_6_beta/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6961d 15h	/t48/tags/rel_0_6_beta/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	6990d 11h	/t48/tags/rel_0_6_beta/
171	remove obsolete output stack_high_o	arniml	6991d 11h	/t48/tags/rel_0_6_beta/
170	intermediate update	arniml	6992d 18h	/t48/tags/rel_0_6_beta/
169	initial check-in	arniml	6992d 23h	/t48/tags/rel_0_6_beta/
168	change address range of wb_master	arniml	6992d 23h	/t48/tags/rel_0_6_beta/
167	simplify address range: - configuration range - Wishbone range	arniml	6992d 23h	/t48/tags/rel_0_6_beta/
166	assign default for state_s	arniml	6994d 15h	/t48/tags/rel_0_6_beta/
165	add component wb_master.vhd	arniml	6995d 14h	/t48/tags/rel_0_6_beta/
164	initial check-in	arniml	6995d 14h	/t48/tags/rel_0_6_beta/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 183

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