URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 25

Rev	Log message	Author	Age	Path
25	initial check-in	arniml	7433d 09h	/t48/tags/rel_0_6_beta/
24	connect control signal for Port 2 expander	arniml	7433d 17h	/t48/tags/rel_0_6_beta/
23	rework Port 2 expander handling	arniml	7433d 17h	/t48/tags/rel_0_6_beta/
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7433d 17h	/t48/tags/rel_0_6_beta/
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7433d 17h	/t48/tags/rel_0_6_beta/
20	move code for PROG out of if-branch for xtal3_s	arniml	7433d 18h	/t48/tags/rel_0_6_beta/
19	enhance simulation result string	arniml	7435d 08h	/t48/tags/rel_0_6_beta/
18	fix constant format	arniml	7435d 08h	/t48/tags/rel_0_6_beta/
17	fix test	arniml	7435d 08h	/t48/tags/rel_0_6_beta/
16	fix header	arniml	7435d 08h	/t48/tags/rel_0_6_beta/
15	initial check-in	arniml	7436d 07h	/t48/tags/rel_0_6_beta/
14	initial check-in	arniml	7436d 08h	/t48/tags/rel_0_6_beta/
12	Imported sources	arniml	7436d 08h	/t48/tags/rel_0_6_beta/
11	add description	arniml	7436d 08h	/t48/tags/rel_0_6_beta/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7437d 07h	/t48/tags/rel_0_6_beta/
9	initial check-in	arniml	7437d 07h	/t48/tags/rel_0_6_beta/
8	initial check-in	arniml	7437d 09h	/t48/tags/rel_0_6_beta/
7	initial check-in	arniml	7437d 09h	/t48/tags/rel_0_6_beta/
6	moved to system directory	arniml	7437d 09h	/t48/tags/rel_0_6_beta/
5	initial check-in	arniml	7438d 09h	/t48/tags/rel_0_6_beta/