URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 55

Rev	Log message	Author	Age	Path
55	add dependency to tb_behav_pack for decoder	arniml	7391d 00h	/t48/tags/rel_0_6_beta/
54	- add tb_istrobe_s	arniml	7391d 00h	/t48/tags/rel_0_6_beta/
53	make istrobe visible through testbench package	arniml	7391d 00h	/t48/tags/rel_0_6_beta/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7391d 00h	/t48/tags/rel_0_6_beta/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7391d 00h	/t48/tags/rel_0_6_beta/
49	Imported sources	arniml	7396d 02h	/t48/tags/rel_0_6_beta/
48	update copyright notice	arniml	7396d 02h	/t48/tags/rel_0_6_beta/
47	initial check-in	arniml	7396d 02h	/t48/tags/rel_0_6_beta/
46	fix test	arniml	7397d 23h	/t48/tags/rel_0_6_beta/
45	remove unused signals	arniml	7397d 23h	/t48/tags/rel_0_6_beta/
44	default assignment for aux_carry_o	arniml	7398d 00h	/t48/tags/rel_0_6_beta/
43	fix sensitivity list	arniml	7399d 01h	/t48/tags/rel_0_6_beta/
42	change test values that match better to the test case	arniml	7399d 03h	/t48/tags/rel_0_6_beta/
41	expand PATH	arniml	7399d 03h	/t48/tags/rel_0_6_beta/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7399d 03h	/t48/tags/rel_0_6_beta/
39	initial check-in	arniml	7401d 07h	/t48/tags/rel_0_6_beta/
38	add measures to implement XCHD	arniml	7401d 07h	/t48/tags/rel_0_6_beta/
37	add dump_compare support	arniml	7401d 07h	/t48/tags/rel_0_6_beta/
36	make calculation of expected value more readable	arniml	7401d 08h	/t48/tags/rel_0_6_beta/
35	initial check-in	arniml	7404d 01h	/t48/tags/rel_0_6_beta/