URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 80

Rev	Log message	Author	Age	Path
80	added if_timing	arniml	7379d 06h	/t48/tags/rel_0_6_beta/
79	add if_timing module	arniml	7379d 06h	/t48/tags/rel_0_6_beta/
78	adjust external timing of BUS	arniml	7379d 06h	/t48/tags/rel_0_6_beta/
77	move from std_logic_arith to numeric_std	arniml	7379d 23h	/t48/tags/rel_0_6_beta/
76	initial check-in	arniml	7380d 03h	/t48/tags/rel_0_6_beta/
75	remove obsolete design unit	arniml	7380d 03h	/t48/tags/rel_0_6_beta/
74	enhance pass/fail detection	arniml	7380d 11h	/t48/tags/rel_0_6_beta/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7380d 11h	/t48/tags/rel_0_6_beta/
72	removed superfluous signal from sensitivity list	arniml	7380d 11h	/t48/tags/rel_0_6_beta/
71	add T8039 and its testbench	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
70	clean test cell before make	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
69	fix name of istrobe	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
68	connect T0 and T1 to P1	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
67	initial check-in	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
66	add temporary workaround for GHDL 0.11	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
65	clean up sensitivity list	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
62	initial check-in	arniml	7386d 04h	/t48/tags/rel_0_6_beta/
61	expand script for dump compare	arniml	7388d 01h	/t48/tags/rel_0_6_beta/