URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [bench/] - Rev 56

Rev	Log message	Author	Age	Path
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7390d 00h	/t48/tags/rel_0_6_beta/bench/
33	rename pX_limp to pX_low_imp	arniml	7406d 01h	/t48/tags/rel_0_6_beta/bench/
30	connect prog_n_o	arniml	7406d 23h	/t48/tags/rel_0_6_beta/bench/
19	enhance simulation result string	arniml	7408d 22h	/t48/tags/rel_0_6_beta/bench/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7410d 21h	/t48/tags/rel_0_6_beta/bench/
8	initial check-in	arniml	7410d 23h	/t48/tags/rel_0_6_beta/bench/