URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 145

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
145	remove PROG and end of XTAL2, see comment for details	arniml	7187d 15h	/t48/tags/rel_0_6_beta/rtl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7187d 15h	/t48/tags/rel_0_6_beta/rtl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7187d 16h	/t48/tags/rel_0_6_beta/rtl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7187d 16h	/t48/tags/rel_0_6_beta/rtl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7189d 02h	/t48/tags/rel_0_6_beta/rtl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7231d 11h	/t48/tags/rel_0_6_beta/rtl/
129	cleanup copyright notice	arniml	7293d 18h	/t48/tags/rel_0_6_beta/rtl/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7300d 22h	/t48/tags/rel_0_6_beta/rtl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7304d 14h	/t48/tags/rel_0_6_beta/rtl/
119	add int_in_progress_o to entity of int module	arniml	7304d 14h	/t48/tags/rel_0_6_beta/rtl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7345d 13h	/t48/tags/rel_0_6_beta/rtl/
107	tie EA to '1'	arniml	7345d 13h	/t48/tags/rel_0_6_beta/rtl/
106	clean-up use of ea_i	arniml	7345d 13h	/t48/tags/rel_0_6_beta/rtl/
101	assert p2_read_p2_o when expander port is read	arniml	7348d 21h	/t48/tags/rel_0_6_beta/rtl/
100	reorder data_o generation	arniml	7348d 21h	/t48/tags/rel_0_6_beta/rtl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7348d 21h	/t48/tags/rel_0_6_beta/rtl/
92	work around bug in Quartus II 4.0	arniml	7349d 20h	/t48/tags/rel_0_6_beta/rtl/
91	fix edge detector bug for counter	arniml	7349d 20h	/t48/tags/rel_0_6_beta/rtl/
86	update notice about expander port instructions	arniml	7364d 23h	/t48/tags/rel_0_6_beta/rtl/
78	adjust external timing of BUS	arniml	7370d 19h	/t48/tags/rel_0_6_beta/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 145

Filtering Options