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[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 172

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Rev	Log message	Author	Age	Path
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7018d 01h	/t48/tags/rel_0_6_beta/rtl/
171	remove obsolete output stack_high_o	arniml	7019d 01h	/t48/tags/rel_0_6_beta/rtl/
169	initial check-in	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
168	change address range of wb_master	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
167	simplify address range: - configuration range - Wishbone range	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
166	assign default for state_s	arniml	7022d 05h	/t48/tags/rel_0_6_beta/rtl/
165	add component wb_master.vhd	arniml	7023d 04h	/t48/tags/rel_0_6_beta/rtl/
164	initial check-in	arniml	7023d 04h	/t48/tags/rel_0_6_beta/rtl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7024d 04h	/t48/tags/rel_0_6_beta/rtl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7055d 08h	/t48/tags/rel_0_6_beta/rtl/
157	removed obsolete constant	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/
156	added hierarchy t8039_notri	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/
155	initial check-in	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7177d 02h	/t48/tags/rel_0_6_beta/rtl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7178d 01h	/t48/tags/rel_0_6_beta/rtl/
149	update	arniml	7178d 01h	/t48/tags/rel_0_6_beta/rtl/
148	initial check-in	arniml	7178d 01h	/t48/tags/rel_0_6_beta/rtl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7215d 03h	/t48/tags/rel_0_6_beta/rtl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7215d 03h	/t48/tags/rel_0_6_beta/rtl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7215d 04h	/t48/tags/rel_0_6_beta/rtl/

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[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 172

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