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[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 183

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Rev	Log message	Author	Age	Path
183	fix missing assignment to outclock	arniml	6898d 06h	/t48/tags/rel_0_6_beta/rtl/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6986d 13h	/t48/tags/rel_0_6_beta/rtl/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6986d 14h	/t48/tags/rel_0_6_beta/rtl/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6988d 01h	/t48/tags/rel_0_6_beta/rtl/
177	Implement db_dir_o glitch-safe	arniml	6988d 01h	/t48/tags/rel_0_6_beta/rtl/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6988d 01h	/t48/tags/rel_0_6_beta/rtl/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6989d 04h	/t48/tags/rel_0_6_beta/rtl/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7018d 01h	/t48/tags/rel_0_6_beta/rtl/
171	remove obsolete output stack_high_o	arniml	7019d 01h	/t48/tags/rel_0_6_beta/rtl/
169	initial check-in	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
168	change address range of wb_master	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
167	simplify address range: - configuration range - Wishbone range	arniml	7020d 13h	/t48/tags/rel_0_6_beta/rtl/
166	assign default for state_s	arniml	7022d 05h	/t48/tags/rel_0_6_beta/rtl/
165	add component wb_master.vhd	arniml	7023d 04h	/t48/tags/rel_0_6_beta/rtl/
164	initial check-in	arniml	7023d 04h	/t48/tags/rel_0_6_beta/rtl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7024d 04h	/t48/tags/rel_0_6_beta/rtl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7055d 08h	/t48/tags/rel_0_6_beta/rtl/
157	removed obsolete constant	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/
156	added hierarchy t8039_notri	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/
155	initial check-in	arniml	7176d 04h	/t48/tags/rel_0_6_beta/rtl/

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[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 183

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