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[/] [t48/] [tags/] [rel_1_0/] - Rev 158

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158 added hierarchies t8039_notri and t8048_notri arniml 7147d 20h /t48/tags/rel_1_0/
157 removed obsolete constant arniml 7147d 21h /t48/tags/rel_1_0/
156 added hierarchy t8039_notri arniml 7147d 21h /t48/tags/rel_1_0/
155 initial check-in arniml 7147d 21h /t48/tags/rel_1_0/
154 added t8039_notri hierarchy arniml 7147d 21h /t48/tags/rel_1_0/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7148d 18h /t48/tags/rel_1_0/
152 added hierarchy t8048_notri and system components package arniml 7149d 09h /t48/tags/rel_1_0/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7149d 09h /t48/tags/rel_1_0/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7149d 17h /t48/tags/rel_1_0/
149 update arniml 7149d 17h /t48/tags/rel_1_0/
148 initial check-in arniml 7149d 17h /t48/tags/rel_1_0/
147 initial check-in for release 0.5 BETA arniml 7185d 19h /t48/tags/rel_1_0/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7186d 19h /t48/tags/rel_1_0/
145 remove PROG and end of XTAL2, see comment for details arniml 7186d 20h /t48/tags/rel_1_0/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7186d 20h /t48/tags/rel_1_0/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7186d 21h /t48/tags/rel_1_0/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7186d 21h /t48/tags/rel_1_0/
141 disable external memory to avoid conflicts with outl a, bus arniml 7186d 21h /t48/tags/rel_1_0/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7186d 21h /t48/tags/rel_1_0/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7188d 07h /t48/tags/rel_1_0/

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