URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 166

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Rev	Log message	Author	Age	Path
166	assign default for state_s	arniml	7037d 06h	/t48/tags/rel_1_0/
165	add component wb_master.vhd	arniml	7038d 05h	/t48/tags/rel_1_0/
164	initial check-in	arniml	7038d 05h	/t48/tags/rel_1_0/
163	add bug Wrong clock applied to T0	arniml	7039d 04h	/t48/tags/rel_1_0/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7039d 05h	/t48/tags/rel_1_0/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7070d 09h	/t48/tags/rel_1_0/
160	add others to case statement	arniml	7191d 05h	/t48/tags/rel_1_0/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7191d 05h	/t48/tags/rel_1_0/
158	added hierarchies t8039_notri and t8048_notri	arniml	7191d 05h	/t48/tags/rel_1_0/
157	removed obsolete constant	arniml	7191d 05h	/t48/tags/rel_1_0/
156	added hierarchy t8039_notri	arniml	7191d 05h	/t48/tags/rel_1_0/
155	initial check-in	arniml	7191d 05h	/t48/tags/rel_1_0/
154	added t8039_notri hierarchy	arniml	7191d 05h	/t48/tags/rel_1_0/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7192d 03h	/t48/tags/rel_1_0/
152	added hierarchy t8048_notri and system components package	arniml	7192d 18h	/t48/tags/rel_1_0/
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7192d 18h	/t48/tags/rel_1_0/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7193d 02h	/t48/tags/rel_1_0/
149	update	arniml	7193d 02h	/t48/tags/rel_1_0/
148	initial check-in	arniml	7193d 02h	/t48/tags/rel_1_0/
147	initial check-in for release 0.5 BETA	arniml	7229d 03h	/t48/tags/rel_1_0/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 166

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