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[/] [t48/] [tags/] [rel_1_0/] - Rev 168

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Rev Log message Author Age Path
168 change address range of wb_master arniml 7029d 10h /t48/tags/rel_1_0/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7029d 10h /t48/tags/rel_1_0/
166 assign default for state_s arniml 7031d 02h /t48/tags/rel_1_0/
165 add component wb_master.vhd arniml 7032d 01h /t48/tags/rel_1_0/
164 initial check-in arniml 7032d 01h /t48/tags/rel_1_0/
163 add bug
Wrong clock applied to T0		 arniml 7033d 00h /t48/tags/rel_1_0/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7033d 00h /t48/tags/rel_1_0/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7064d 05h /t48/tags/rel_1_0/
160 add others to case statement arniml 7185d 01h /t48/tags/rel_1_0/
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7185d 01h /t48/tags/rel_1_0/
158 added hierarchies t8039_notri and t8048_notri arniml 7185d 01h /t48/tags/rel_1_0/
157 removed obsolete constant arniml 7185d 01h /t48/tags/rel_1_0/
156 added hierarchy t8039_notri arniml 7185d 01h /t48/tags/rel_1_0/
155 initial check-in arniml 7185d 01h /t48/tags/rel_1_0/
154 added t8039_notri hierarchy arniml 7185d 01h /t48/tags/rel_1_0/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7185d 22h /t48/tags/rel_1_0/
152 added hierarchy t8048_notri and system components package arniml 7186d 13h /t48/tags/rel_1_0/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7186d 13h /t48/tags/rel_1_0/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7186d 21h /t48/tags/rel_1_0/
149 update arniml 7186d 21h /t48/tags/rel_1_0/

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