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[/] [t48/] [tags/] [rel_1_0/] - Rev 173

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Rev	Log message	Author	Age	Path
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7003d 20h	/t48/tags/rel_1_0/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7032d 16h	/t48/tags/rel_1_0/
171	remove obsolete output stack_high_o	arniml	7033d 17h	/t48/tags/rel_1_0/
170	intermediate update	arniml	7034d 23h	/t48/tags/rel_1_0/
169	initial check-in	arniml	7035d 04h	/t48/tags/rel_1_0/
168	change address range of wb_master	arniml	7035d 04h	/t48/tags/rel_1_0/
167	simplify address range: - configuration range - Wishbone range	arniml	7035d 04h	/t48/tags/rel_1_0/
166	assign default for state_s	arniml	7036d 20h	/t48/tags/rel_1_0/
165	add component wb_master.vhd	arniml	7037d 19h	/t48/tags/rel_1_0/
164	initial check-in	arniml	7037d 19h	/t48/tags/rel_1_0/
163	add bug Wrong clock applied to T0	arniml	7038d 19h	/t48/tags/rel_1_0/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7038d 19h	/t48/tags/rel_1_0/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7069d 23h	/t48/tags/rel_1_0/
160	add others to case statement	arniml	7190d 19h	/t48/tags/rel_1_0/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7190d 19h	/t48/tags/rel_1_0/
158	added hierarchies t8039_notri and t8048_notri	arniml	7190d 19h	/t48/tags/rel_1_0/
157	removed obsolete constant	arniml	7190d 19h	/t48/tags/rel_1_0/
156	added hierarchy t8039_notri	arniml	7190d 19h	/t48/tags/rel_1_0/
155	initial check-in	arniml	7190d 19h	/t48/tags/rel_1_0/
154	added t8039_notri hierarchy	arniml	7190d 19h	/t48/tags/rel_1_0/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 173

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