OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 189

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6911d 06h /t48/tags/rel_1_0/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6911d 06h /t48/tags/rel_1_0/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6911d 06h /t48/tags/rel_1_0/
186 update to version 0.2 arniml 6912d 08h /t48/tags/rel_1_0/
185 initial check-in arniml 6917d 06h /t48/tags/rel_1_0/
184 initial check-in arniml 6917d 07h /t48/tags/rel_1_0/
183 fix missing assignment to outclock arniml 6917d 10h /t48/tags/rel_1_0/
182 intermediate version arniml 6997d 09h /t48/tags/rel_1_0/
181 fix typo arniml 6997d 12h /t48/tags/rel_1_0/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7005d 17h /t48/tags/rel_1_0/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7005d 17h /t48/tags/rel_1_0/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7007d 05h /t48/tags/rel_1_0/
177 Implement db_dir_o glitch-safe arniml 7007d 05h /t48/tags/rel_1_0/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7007d 05h /t48/tags/rel_1_0/
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7008d 08h /t48/tags/rel_1_0/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7008d 08h /t48/tags/rel_1_0/
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7008d 08h /t48/tags/rel_1_0/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7037d 05h /t48/tags/rel_1_0/
171 remove obsolete output stack_high_o arniml 7038d 05h /t48/tags/rel_1_0/
170 intermediate update arniml 7039d 12h /t48/tags/rel_1_0/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.