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[/] [t48/] [tags/] [rel_1_0/] - Rev 40

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Rev Log message Author Age Path
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7405d 04h /t48/tags/rel_1_0/
39 initial check-in arniml 7407d 08h /t48/tags/rel_1_0/
38 add measures to implement XCHD arniml 7407d 08h /t48/tags/rel_1_0/
37 add dump_compare support arniml 7407d 08h /t48/tags/rel_1_0/
36 make calculation of expected value more readable arniml 7407d 09h /t48/tags/rel_1_0/
35 initial check-in arniml 7410d 02h /t48/tags/rel_1_0/
34 fix test wrt AC arniml 7413d 02h /t48/tags/rel_1_0/
33 rename pX_limp to pX_low_imp arniml 7413d 02h /t48/tags/rel_1_0/
32 rename pX_limp to pX_low_imp arniml 7413d 02h /t48/tags/rel_1_0/
31 refer PROJECT_DIR variable arniml 7413d 02h /t48/tags/rel_1_0/
30 connect prog_n_o arniml 7414d 01h /t48/tags/rel_1_0/
29 take auxiliary carry from direct ALU connection arniml 7414d 01h /t48/tags/rel_1_0/
28 update wiring for DA support arniml 7414d 01h /t48/tags/rel_1_0/
27 implemented mnemonic DA arniml 7414d 01h /t48/tags/rel_1_0/
26 support for DA instruction arniml 7414d 01h /t48/tags/rel_1_0/
25 initial check-in arniml 7414d 01h /t48/tags/rel_1_0/
24 connect control signal for Port 2 expander arniml 7414d 09h /t48/tags/rel_1_0/
23 rework Port 2 expander handling arniml 7414d 09h /t48/tags/rel_1_0/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7414d 09h /t48/tags/rel_1_0/
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A		 arniml 7414d 09h /t48/tags/rel_1_0/

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