URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 41

Rev	Log message	Author	Age	Path
41	expand PATH	arniml	7404d 23h	/t48/tags/rel_1_0/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7404d 23h	/t48/tags/rel_1_0/
39	initial check-in	arniml	7407d 03h	/t48/tags/rel_1_0/
38	add measures to implement XCHD	arniml	7407d 03h	/t48/tags/rel_1_0/
37	add dump_compare support	arniml	7407d 03h	/t48/tags/rel_1_0/
36	make calculation of expected value more readable	arniml	7407d 04h	/t48/tags/rel_1_0/
35	initial check-in	arniml	7409d 21h	/t48/tags/rel_1_0/
34	fix test wrt AC	arniml	7412d 21h	/t48/tags/rel_1_0/
33	rename pX_limp to pX_low_imp	arniml	7412d 22h	/t48/tags/rel_1_0/
32	rename pX_limp to pX_low_imp	arniml	7412d 22h	/t48/tags/rel_1_0/
31	refer PROJECT_DIR variable	arniml	7412d 22h	/t48/tags/rel_1_0/
30	connect prog_n_o	arniml	7413d 20h	/t48/tags/rel_1_0/
29	take auxiliary carry from direct ALU connection	arniml	7413d 20h	/t48/tags/rel_1_0/
28	update wiring for DA support	arniml	7413d 20h	/t48/tags/rel_1_0/
27	implemented mnemonic DA	arniml	7413d 20h	/t48/tags/rel_1_0/
26	support for DA instruction	arniml	7413d 20h	/t48/tags/rel_1_0/
25	initial check-in	arniml	7413d 20h	/t48/tags/rel_1_0/
24	connect control signal for Port 2 expander	arniml	7414d 04h	/t48/tags/rel_1_0/
23	rework Port 2 expander handling	arniml	7414d 04h	/t48/tags/rel_1_0/
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7414d 04h	/t48/tags/rel_1_0/