URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 53

Rev	Log message	Author	Age	Path
53	make istrobe visible through testbench package	arniml	7396d 17h	/t48/tags/rel_1_0/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7396d 17h	/t48/tags/rel_1_0/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7396d 17h	/t48/tags/rel_1_0/
49	Imported sources	arniml	7401d 19h	/t48/tags/rel_1_0/
48	update copyright notice	arniml	7401d 19h	/t48/tags/rel_1_0/
47	initial check-in	arniml	7401d 19h	/t48/tags/rel_1_0/
46	fix test	arniml	7403d 16h	/t48/tags/rel_1_0/
45	remove unused signals	arniml	7403d 16h	/t48/tags/rel_1_0/
44	default assignment for aux_carry_o	arniml	7403d 17h	/t48/tags/rel_1_0/
43	fix sensitivity list	arniml	7404d 18h	/t48/tags/rel_1_0/
42	change test values that match better to the test case	arniml	7404d 20h	/t48/tags/rel_1_0/
41	expand PATH	arniml	7404d 20h	/t48/tags/rel_1_0/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7404d 20h	/t48/tags/rel_1_0/
39	initial check-in	arniml	7407d 00h	/t48/tags/rel_1_0/
38	add measures to implement XCHD	arniml	7407d 00h	/t48/tags/rel_1_0/
37	add dump_compare support	arniml	7407d 00h	/t48/tags/rel_1_0/
36	make calculation of expected value more readable	arniml	7407d 01h	/t48/tags/rel_1_0/
35	initial check-in	arniml	7409d 18h	/t48/tags/rel_1_0/
34	fix test wrt AC	arniml	7412d 18h	/t48/tags/rel_1_0/
33	rename pX_limp to pX_low_imp	arniml	7412d 18h	/t48/tags/rel_1_0/