URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 78

Rev	Log message	Author	Age	Path
78	adjust external timing of BUS	arniml	7385d 09h	/t48/tags/rel_1_0/
77	move from std_logic_arith to numeric_std	arniml	7386d 02h	/t48/tags/rel_1_0/
76	initial check-in	arniml	7386d 06h	/t48/tags/rel_1_0/
75	remove obsolete design unit	arniml	7386d 06h	/t48/tags/rel_1_0/
74	enhance pass/fail detection	arniml	7386d 14h	/t48/tags/rel_1_0/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7386d 14h	/t48/tags/rel_1_0/
72	removed superfluous signal from sensitivity list	arniml	7386d 14h	/t48/tags/rel_1_0/
71	add T8039 and its testbench	arniml	7392d 07h	/t48/tags/rel_1_0/
70	clean test cell before make	arniml	7392d 07h	/t48/tags/rel_1_0/
69	fix name of istrobe	arniml	7392d 07h	/t48/tags/rel_1_0/
68	connect T0 and T1 to P1	arniml	7392d 07h	/t48/tags/rel_1_0/
67	initial check-in	arniml	7392d 07h	/t48/tags/rel_1_0/
66	add temporary workaround for GHDL 0.11	arniml	7392d 07h	/t48/tags/rel_1_0/
65	clean up sensitivity list	arniml	7392d 07h	/t48/tags/rel_1_0/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7392d 07h	/t48/tags/rel_1_0/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7392d 07h	/t48/tags/rel_1_0/
62	initial check-in	arniml	7392d 07h	/t48/tags/rel_1_0/
61	expand script for dump compare	arniml	7394d 03h	/t48/tags/rel_1_0/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7395d 04h	/t48/tags/rel_1_0/
59	increment prescaler with MSTATE4	arniml	7395d 04h	/t48/tags/rel_1_0/