URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_1_0/] [bench/] - Rev 202

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Rev	Log message	Author	Age	Path
202	fix address assignment	arniml	6832d 11h	/t48/tags/rel_1_0/bench/
201	split low impedance markers for P2	arniml	6832d 11h	/t48/tags/rel_1_0/bench/
200	add check for tCP: Port Control Setup to PROG'	arniml	6832d 11h	/t48/tags/rel_1_0/bench/
183	fix missing assignment to outclock	arniml	6887d 15h	/t48/tags/rel_1_0/bench/
160	add others to case statement	arniml	7165d 12h	/t48/tags/rel_1_0/bench/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7204d 13h	/t48/tags/rel_1_0/bench/
133	add checks for PSEN	arniml	7248d 08h	/t48/tags/rel_1_0/bench/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7361d 21h	/t48/tags/rel_1_0/bench/
110	exchange syn_rom for lpm_rom	arniml	7361d 21h	/t48/tags/rel_1_0/bench/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7365d 18h	/t48/tags/rel_1_0/bench/
83	connect if_timing to P2 output of T48	arniml	7387d 12h	/t48/tags/rel_1_0/bench/
82	check expander timings	arniml	7387d 12h	/t48/tags/rel_1_0/bench/
81	initial check-in	arniml	7387d 16h	/t48/tags/rel_1_0/bench/
80	added if_timing	arniml	7387d 16h	/t48/tags/rel_1_0/bench/
68	connect T0 and T1 to P1	arniml	7394d 13h	/t48/tags/rel_1_0/bench/
67	initial check-in	arniml	7394d 13h	/t48/tags/rel_1_0/bench/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7398d 11h	/t48/tags/rel_1_0/bench/
33	rename pX_limp to pX_low_imp	arniml	7414d 13h	/t48/tags/rel_1_0/bench/
30	connect prog_n_o	arniml	7415d 11h	/t48/tags/rel_1_0/bench/
19	enhance simulation result string	arniml	7417d 10h	/t48/tags/rel_1_0/bench/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [bench/] - Rev 202

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