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[/] [t48/] [tags/] [rel_1_0/] [bench/] - Rev 293

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5563d 21h	/t48/tags/rel_1_0/bench/
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6376d 07h	/t48/tags/rel_1_0/bench/
248	initial check-in	arniml	6534d 06h	/t48/tags/rel_1_0/bench/
247	initial check-in	arniml	6534d 08h	/t48/tags/rel_1_0/bench/
240	comment added about lower 1k of external ROM	arniml	6554d 06h	/t48/tags/rel_1_0/bench/
234	cleanup & enhance external access	arniml	6556d 06h	/t48/tags/rel_1_0/bench/
233	added external ROM	arniml	6556d 06h	/t48/tags/rel_1_0/bench/
228	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom	arniml	6557d 05h	/t48/tags/rel_1_0/bench/
224	initial check-in	arniml	6557d 06h	/t48/tags/rel_1_0/bench/
220	new input xtal_en_i	arniml	6558d 06h	/t48/tags/rel_1_0/bench/
202	fix address assignment	arniml	6788d 09h	/t48/tags/rel_1_0/bench/
201	split low impedance markers for P2	arniml	6788d 09h	/t48/tags/rel_1_0/bench/
200	add check for tCP: Port Control Setup to PROG'	arniml	6788d 09h	/t48/tags/rel_1_0/bench/
183	fix missing assignment to outclock	arniml	6843d 13h	/t48/tags/rel_1_0/bench/
160	add others to case statement	arniml	7121d 11h	/t48/tags/rel_1_0/bench/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7160d 11h	/t48/tags/rel_1_0/bench/
133	add checks for PSEN	arniml	7204d 06h	/t48/tags/rel_1_0/bench/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7317d 19h	/t48/tags/rel_1_0/bench/
110	exchange syn_rom for lpm_rom	arniml	7317d 19h	/t48/tags/rel_1_0/bench/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7321d 16h	/t48/tags/rel_1_0/bench/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [bench/] - Rev 293

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