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[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] - Rev 202

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Rev Log message Author Age Path
202 fix address assignment arniml 6833d 03h /t48/tags/rel_1_0/bench/vhdl/
201 split low impedance markers for P2 arniml 6833d 03h /t48/tags/rel_1_0/bench/vhdl/
200 add check for
tCP: Port Control Setup to PROG'
arniml 6833d 03h /t48/tags/rel_1_0/bench/vhdl/
183 fix missing assignment to outclock arniml 6888d 07h /t48/tags/rel_1_0/bench/vhdl/
160 add others to case statement arniml 7166d 05h /t48/tags/rel_1_0/bench/vhdl/
140 remove tAW sanity check
conflicts with OUTL A, BUS
arniml 7205d 05h /t48/tags/rel_1_0/bench/vhdl/
133 add checks for PSEN arniml 7249d 00h /t48/tags/rel_1_0/bench/vhdl/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly
arniml 7362d 13h /t48/tags/rel_1_0/bench/vhdl/
110 exchange syn_rom for lpm_rom arniml 7362d 13h /t48/tags/rel_1_0/bench/vhdl/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data
arniml 7366d 10h /t48/tags/rel_1_0/bench/vhdl/
83 connect if_timing to P2 output of T48 arniml 7388d 04h /t48/tags/rel_1_0/bench/vhdl/
82 check expander timings arniml 7388d 04h /t48/tags/rel_1_0/bench/vhdl/
81 initial check-in arniml 7388d 08h /t48/tags/rel_1_0/bench/vhdl/
80 added if_timing arniml 7388d 08h /t48/tags/rel_1_0/bench/vhdl/
68 connect T0 and T1 to P1 arniml 7395d 05h /t48/tags/rel_1_0/bench/vhdl/
67 initial check-in arniml 7395d 05h /t48/tags/rel_1_0/bench/vhdl/
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator
arniml 7399d 04h /t48/tags/rel_1_0/bench/vhdl/
33 rename pX_limp to pX_low_imp arniml 7415d 05h /t48/tags/rel_1_0/bench/vhdl/
30 connect prog_n_o arniml 7416d 03h /t48/tags/rel_1_0/bench/vhdl/
19 enhance simulation result string arniml 7418d 02h /t48/tags/rel_1_0/bench/vhdl/

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