URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5590d 21h	/t48/tags/rel_1_0/bench/vhdl/
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6403d 08h	/t48/tags/rel_1_0/bench/vhdl/
248	initial check-in	arniml	6561d 06h	/t48/tags/rel_1_0/bench/vhdl/
247	initial check-in	arniml	6561d 08h	/t48/tags/rel_1_0/bench/vhdl/
240	comment added about lower 1k of external ROM	arniml	6581d 06h	/t48/tags/rel_1_0/bench/vhdl/
234	cleanup & enhance external access	arniml	6583d 07h	/t48/tags/rel_1_0/bench/vhdl/
233	added external ROM	arniml	6583d 07h	/t48/tags/rel_1_0/bench/vhdl/
228	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom	arniml	6584d 06h	/t48/tags/rel_1_0/bench/vhdl/
224	initial check-in	arniml	6584d 06h	/t48/tags/rel_1_0/bench/vhdl/
220	new input xtal_en_i	arniml	6585d 06h	/t48/tags/rel_1_0/bench/vhdl/
202	fix address assignment	arniml	6815d 10h	/t48/tags/rel_1_0/bench/vhdl/
201	split low impedance markers for P2	arniml	6815d 10h	/t48/tags/rel_1_0/bench/vhdl/
200	add check for tCP: Port Control Setup to PROG'	arniml	6815d 10h	/t48/tags/rel_1_0/bench/vhdl/
183	fix missing assignment to outclock	arniml	6870d 14h	/t48/tags/rel_1_0/bench/vhdl/
160	add others to case statement	arniml	7148d 11h	/t48/tags/rel_1_0/bench/vhdl/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7187d 12h	/t48/tags/rel_1_0/bench/vhdl/
133	add checks for PSEN	arniml	7231d 07h	/t48/tags/rel_1_0/bench/vhdl/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7344d 20h	/t48/tags/rel_1_0/bench/vhdl/
110	exchange syn_rom for lpm_rom	arniml	7344d 20h	/t48/tags/rel_1_0/bench/vhdl/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7348d 17h	/t48/tags/rel_1_0/bench/vhdl/

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[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] - Rev 292

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