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[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 149

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Rev	Log message	Author	Age	Path
149	update	arniml	7186d 17h	/t48/tags/rel_1_0/rtl/
148	initial check-in	arniml	7186d 17h	/t48/tags/rel_1_0/rtl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7223d 20h	/t48/tags/rel_1_0/rtl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7223d 20h	/t48/tags/rel_1_0/rtl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7223d 21h	/t48/tags/rel_1_0/rtl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7223d 21h	/t48/tags/rel_1_0/rtl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7225d 07h	/t48/tags/rel_1_0/rtl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7267d 16h	/t48/tags/rel_1_0/rtl/
129	cleanup copyright notice	arniml	7330d 00h	/t48/tags/rel_1_0/rtl/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7337d 03h	/t48/tags/rel_1_0/rtl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7340d 19h	/t48/tags/rel_1_0/rtl/
119	add int_in_progress_o to entity of int module	arniml	7340d 19h	/t48/tags/rel_1_0/rtl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7381d 18h	/t48/tags/rel_1_0/rtl/
107	tie EA to '1'	arniml	7381d 19h	/t48/tags/rel_1_0/rtl/
106	clean-up use of ea_i	arniml	7381d 19h	/t48/tags/rel_1_0/rtl/
101	assert p2_read_p2_o when expander port is read	arniml	7385d 02h	/t48/tags/rel_1_0/rtl/
100	reorder data_o generation	arniml	7385d 02h	/t48/tags/rel_1_0/rtl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7385d 03h	/t48/tags/rel_1_0/rtl/
92	work around bug in Quartus II 4.0	arniml	7386d 01h	/t48/tags/rel_1_0/rtl/
91	fix edge detector bug for counter	arniml	7386d 01h	/t48/tags/rel_1_0/rtl/

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 149

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