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[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 227

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227 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom arniml 6595d 22h /t48/tags/rel_1_0/rtl/
226 replaced syn_ram with generic_ram_ena arniml 6595d 22h /t48/tags/rel_1_0/rtl/
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6595d 22h /t48/tags/rel_1_0/rtl/
224 initial check-in arniml 6595d 22h /t48/tags/rel_1_0/rtl/
222 add note about clock enable for data memory RAM macro arniml 6596d 22h /t48/tags/rel_1_0/rtl/
221 new input xtal_en_i arniml 6596d 22h /t48/tags/rel_1_0/rtl/
220 new input xtal_en_i arniml 6596d 22h /t48/tags/rel_1_0/rtl/
219 new input xtal_en_i gates xtal_i base clock arniml 6596d 22h /t48/tags/rel_1_0/rtl/
216 assign clk_i to outclock arniml 6814d 02h /t48/tags/rel_1_0/rtl/
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory
arniml 6814d 02h /t48/tags/rel_1_0/rtl/
214 fix sensitivity list arniml 6821d 04h /t48/tags/rel_1_0/rtl/
213 properly drive P1 and P2 with low impedance markers arniml 6825d 23h /t48/tags/rel_1_0/rtl/
211 wire signals for P2 low impedance marker issue arniml 6827d 01h /t48/tags/rel_1_0/rtl/
210 entity changes for P2 low impedance marker issue arniml 6827d 01h /t48/tags/rel_1_0/rtl/
209 entity changes for P2 low impedance issue arniml 6827d 01h /t48/tags/rel_1_0/rtl/
208 wire signals for P2 low impeddance marker issue arniml 6827d 01h /t48/tags/rel_1_0/rtl/
207 entity changes for P2 low impedance trigger issue arniml 6827d 02h /t48/tags/rel_1_0/rtl/
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads
arniml 6827d 02h /t48/tags/rel_1_0/rtl/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6827d 02h /t48/tags/rel_1_0/rtl/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module
arniml 6827d 02h /t48/tags/rel_1_0/rtl/

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