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[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 292

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Rev Log message Author Age Path
292 New directory structure. root 5570d 05h /t48/tags/rel_1_0/rtl/
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6382d 16h /t48/tags/rel_1_0/rtl/
275 fix sensitivity list arniml 6383d 14h /t48/tags/rel_1_0/rtl/
273 reset counter_q arniml 6401d 01h /t48/tags/rel_1_0/rtl/
272 fix entity port names arniml 6405d 02h /t48/tags/rel_1_0/rtl/
271 initial check-in arniml 6405d 02h /t48/tags/rel_1_0/rtl/
270 fix component name arniml 6405d 03h /t48/tags/rel_1_0/rtl/
262 name keyword added arniml 6540d 14h /t48/tags/rel_1_0/rtl/
261 * name tag added
* restriction concerning expander port removed
arniml 6540d 14h /t48/tags/rel_1_0/rtl/
249 Fix bug report
"Deassertion of PROG too early"
PROG is deasserted at end of XTAL3 now
arniml 6540d 14h /t48/tags/rel_1_0/rtl/
247 initial check-in arniml 6540d 16h /t48/tags/rel_1_0/rtl/
231 obsoleted by new memory concept arniml 6563d 14h /t48/tags/rel_1_0/rtl/
227 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom arniml 6563d 14h /t48/tags/rel_1_0/rtl/
226 replaced syn_ram with generic_ram_ena arniml 6563d 14h /t48/tags/rel_1_0/rtl/
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6563d 14h /t48/tags/rel_1_0/rtl/
224 initial check-in arniml 6563d 14h /t48/tags/rel_1_0/rtl/
222 add note about clock enable for data memory RAM macro arniml 6564d 14h /t48/tags/rel_1_0/rtl/
221 new input xtal_en_i arniml 6564d 14h /t48/tags/rel_1_0/rtl/
220 new input xtal_en_i arniml 6564d 14h /t48/tags/rel_1_0/rtl/
219 new input xtal_en_i gates xtal_i base clock arniml 6564d 14h /t48/tags/rel_1_0/rtl/

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