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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 143

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Rev	Log message	Author	Age	Path
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7198d 04h	/t48/tags/rel_1_0/rtl/vhdl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7198d 04h	/t48/tags/rel_1_0/rtl/vhdl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7199d 15h	/t48/tags/rel_1_0/rtl/vhdl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7241d 23h	/t48/tags/rel_1_0/rtl/vhdl/
129	cleanup copyright notice	arniml	7304d 07h	/t48/tags/rel_1_0/rtl/vhdl/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7311d 11h	/t48/tags/rel_1_0/rtl/vhdl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7315d 03h	/t48/tags/rel_1_0/rtl/vhdl/
119	add int_in_progress_o to entity of int module	arniml	7315d 03h	/t48/tags/rel_1_0/rtl/vhdl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7356d 02h	/t48/tags/rel_1_0/rtl/vhdl/
107	tie EA to '1'	arniml	7356d 02h	/t48/tags/rel_1_0/rtl/vhdl/
106	clean-up use of ea_i	arniml	7356d 02h	/t48/tags/rel_1_0/rtl/vhdl/
101	assert p2_read_p2_o when expander port is read	arniml	7359d 09h	/t48/tags/rel_1_0/rtl/vhdl/
100	reorder data_o generation	arniml	7359d 09h	/t48/tags/rel_1_0/rtl/vhdl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7359d 10h	/t48/tags/rel_1_0/rtl/vhdl/
92	work around bug in Quartus II 4.0	arniml	7360d 08h	/t48/tags/rel_1_0/rtl/vhdl/
91	fix edge detector bug for counter	arniml	7360d 08h	/t48/tags/rel_1_0/rtl/vhdl/
86	update notice about expander port instructions	arniml	7375d 12h	/t48/tags/rel_1_0/rtl/vhdl/
78	adjust external timing of BUS	arniml	7381d 08h	/t48/tags/rel_1_0/rtl/vhdl/
77	move from std_logic_arith to numeric_std	arniml	7382d 00h	/t48/tags/rel_1_0/rtl/vhdl/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7382d 13h	/t48/tags/rel_1_0/rtl/vhdl/

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 143

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