URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5590d 22h	/t48/tags/rel_1_0/rtl/vhdl/
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6403d 08h	/t48/tags/rel_1_0/rtl/vhdl/
275	fix sensitivity list	arniml	6404d 06h	/t48/tags/rel_1_0/rtl/vhdl/
273	reset counter_q	arniml	6421d 17h	/t48/tags/rel_1_0/rtl/vhdl/
272	fix entity port names	arniml	6425d 19h	/t48/tags/rel_1_0/rtl/vhdl/
271	initial check-in	arniml	6425d 19h	/t48/tags/rel_1_0/rtl/vhdl/
270	fix component name	arniml	6425d 19h	/t48/tags/rel_1_0/rtl/vhdl/
262	name keyword added	arniml	6561d 06h	/t48/tags/rel_1_0/rtl/vhdl/
261	* name tag added * restriction concerning expander port removed	arniml	6561d 06h	/t48/tags/rel_1_0/rtl/vhdl/
249	Fix bug report "Deassertion of PROG too early" PROG is deasserted at end of XTAL3 now	arniml	6561d 06h	/t48/tags/rel_1_0/rtl/vhdl/
247	initial check-in	arniml	6561d 08h	/t48/tags/rel_1_0/rtl/vhdl/
231	obsoleted by new memory concept	arniml	6584d 06h	/t48/tags/rel_1_0/rtl/vhdl/
227	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom	arniml	6584d 06h	/t48/tags/rel_1_0/rtl/vhdl/
226	replaced syn_ram with generic_ram_ena	arniml	6584d 06h	/t48/tags/rel_1_0/rtl/vhdl/
225	replaced syn_rom and syn_ram with t48_rom and generic_ram_ena	arniml	6584d 06h	/t48/tags/rel_1_0/rtl/vhdl/
224	initial check-in	arniml	6584d 06h	/t48/tags/rel_1_0/rtl/vhdl/
222	add note about clock enable for data memory RAM macro	arniml	6585d 06h	/t48/tags/rel_1_0/rtl/vhdl/
221	new input xtal_en_i	arniml	6585d 06h	/t48/tags/rel_1_0/rtl/vhdl/
220	new input xtal_en_i	arniml	6585d 07h	/t48/tags/rel_1_0/rtl/vhdl/
219	new input xtal_en_i gates xtal_i base clock	arniml	6585d 07h	/t48/tags/rel_1_0/rtl/vhdl/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 292

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