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[/] [t48/] [tags/] [rel_1_1/] - Rev 117

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Rev Log message Author Age Path
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7341d 13h /t48/tags/rel_1_1/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7369d 13h /t48/tags/rel_1_1/
115 extend description arniml 7370d 17h /t48/tags/rel_1_1/
114 initial check-in arniml 7374d 13h /t48/tags/rel_1_1/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7380d 22h /t48/tags/rel_1_1/
112 update tb_behav_c0 for new ROM layout arniml 7380d 22h /t48/tags/rel_1_1/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7380d 22h /t48/tags/rel_1_1/
110 exchange syn_rom for lpm_rom arniml 7380d 22h /t48/tags/rel_1_1/
109 add new bug for release 0.1 BETA arniml 7381d 11h /t48/tags/rel_1_1/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7381d 12h /t48/tags/rel_1_1/
107 tie EA to '1' arniml 7381d 12h /t48/tags/rel_1_1/
106 clean-up use of ea_i arniml 7381d 12h /t48/tags/rel_1_1/
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7383d 21h /t48/tags/rel_1_1/
104 add white_box directory to test suite arniml 7384d 19h /t48/tags/rel_1_1/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7384d 19h /t48/tags/rel_1_1/
102 update for changes in address space of external memory arniml 7384d 19h /t48/tags/rel_1_1/
101 assert p2_read_p2_o when expander port is read arniml 7384d 19h /t48/tags/rel_1_1/
100 reorder data_o generation arniml 7384d 19h /t48/tags/rel_1_1/
99 initial check-in arniml 7384d 19h /t48/tags/rel_1_1/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7384d 20h /t48/tags/rel_1_1/

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