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[/] [t48/] [tags/] [rel_1_1/] - Rev 182

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Rev	Log message	Author	Age	Path
182	intermediate version	arniml	6992d 22h	/t48/tags/rel_1_1/
181	fix typo	arniml	6993d 01h	/t48/tags/rel_1_1/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	7001d 06h	/t48/tags/rel_1_1/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	7001d 07h	/t48/tags/rel_1_1/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	7002d 18h	/t48/tags/rel_1_1/
177	Implement db_dir_o glitch-safe	arniml	7002d 18h	/t48/tags/rel_1_1/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	7002d 18h	/t48/tags/rel_1_1/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	7003d 21h	/t48/tags/rel_1_1/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	7003d 21h	/t48/tags/rel_1_1/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7003d 22h	/t48/tags/rel_1_1/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7032d 18h	/t48/tags/rel_1_1/
171	remove obsolete output stack_high_o	arniml	7033d 18h	/t48/tags/rel_1_1/
170	intermediate update	arniml	7035d 01h	/t48/tags/rel_1_1/
169	initial check-in	arniml	7035d 06h	/t48/tags/rel_1_1/
168	change address range of wb_master	arniml	7035d 06h	/t48/tags/rel_1_1/
167	simplify address range: - configuration range - Wishbone range	arniml	7035d 06h	/t48/tags/rel_1_1/
166	assign default for state_s	arniml	7036d 22h	/t48/tags/rel_1_1/
165	add component wb_master.vhd	arniml	7037d 21h	/t48/tags/rel_1_1/
164	initial check-in	arniml	7037d 21h	/t48/tags/rel_1_1/
163	add bug Wrong clock applied to T0	arniml	7038d 20h	/t48/tags/rel_1_1/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 182

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