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[/] [t48/] [tags/] [rel_1_1/] - Rev 206

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206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6892d 08h /t48/tags/rel_1_1/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6892d 09h /t48/tags/rel_1_1/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6892d 09h /t48/tags/rel_1_1/
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6892d 09h /t48/tags/rel_1_1/
202 fix address assignment arniml 6892d 09h /t48/tags/rel_1_1/
201 split low impedance markers for P2 arniml 6892d 09h /t48/tags/rel_1_1/
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6892d 09h /t48/tags/rel_1_1/
199 initial check-in arniml 6892d 09h /t48/tags/rel_1_1/
198 fix package dependencies arniml 6892d 13h /t48/tags/rel_1_1/
197 preliminary version 0.3 arniml 6893d 16h /t48/tags/rel_1_1/
196 update to version 0.3 arniml 6893d 16h /t48/tags/rel_1_1/
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6893d 20h /t48/tags/rel_1_1/
194 initial check-in arniml 6893d 20h /t48/tags/rel_1_1/
193 iManual arniml 6908d 22h /t48/tags/rel_1_1/
192 update list for Wishbone toplevel arniml 6909d 09h /t48/tags/rel_1_1/
191 preliminary version 0.2 arniml 6909d 12h /t48/tags/rel_1_1/
190 finalize change log for release 0.6 beta arniml 6910d 07h /t48/tags/rel_1_1/
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6941d 08h /t48/tags/rel_1_1/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6941d 09h /t48/tags/rel_1_1/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6941d 09h /t48/tags/rel_1_1/

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