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[/] [t48/] [tags/] [rel_1_1/] - Rev 222

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Rev	Log message	Author	Age	Path
222	add note about clock enable for data memory RAM macro	arniml	6627d 04h	/t48/tags/rel_1_1/
221	new input xtal_en_i	arniml	6627d 04h	/t48/tags/rel_1_1/
220	new input xtal_en_i	arniml	6627d 04h	/t48/tags/rel_1_1/
219	new input xtal_en_i gates xtal_i base clock	arniml	6627d 04h	/t48/tags/rel_1_1/
218	simplifications	arniml	6713d 11h	/t48/tags/rel_1_1/
217	update for release 0.6.1 beta	arniml	6782d 08h	/t48/tags/rel_1_1/
216	assign clk_i to outclock	arniml	6844d 08h	/t48/tags/rel_1_1/
215	suppress p2_output_pch_o when MOVX operation is accessing the external memory	arniml	6844d 08h	/t48/tags/rel_1_1/
214	fix sensitivity list	arniml	6851d 09h	/t48/tags/rel_1_1/
213	properly drive P1 and P2 with low impedance markers	arniml	6856d 05h	/t48/tags/rel_1_1/
212	add bug reports "Problem when INT and JMP" "P2 Port value restored after expander access"	arniml	6856d 08h	/t48/tags/rel_1_1/
211	wire signals for P2 low impedance marker issue	arniml	6857d 07h	/t48/tags/rel_1_1/
210	entity changes for P2 low impedance marker issue	arniml	6857d 07h	/t48/tags/rel_1_1/
209	entity changes for P2 low impedance issue	arniml	6857d 07h	/t48/tags/rel_1_1/
208	wire signals for P2 low impeddance marker issue	arniml	6857d 07h	/t48/tags/rel_1_1/
207	entity changes for P2 low impedance trigger issue	arniml	6857d 07h	/t48/tags/rel_1_1/
206	* change low impedance markers for P2 separate marker for low and high part * p2_o output is also registered to prevent combinational output to pads	arniml	6857d 07h	/t48/tags/rel_1_1/
205	operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3	arniml	6857d 07h	/t48/tags/rel_1_1/
204	* suppress p2_output_pch_o when p2_output_exp is active * wire xtal_i to interrupt module	arniml	6857d 07h	/t48/tags/rel_1_1/
203	* shift assertion of ALE and PROG to xtal3 * correct change of revision 1.8	arniml	6857d 07h	/t48/tags/rel_1_1/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 222

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