URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 24

Rev	Log message	Author	Age	Path
24	connect control signal for Port 2 expander	arniml	7412d 07h	/t48/tags/rel_1_1/
23	rework Port 2 expander handling	arniml	7412d 07h	/t48/tags/rel_1_1/
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7412d 07h	/t48/tags/rel_1_1/
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7412d 07h	/t48/tags/rel_1_1/
20	move code for PROG out of if-branch for xtal3_s	arniml	7412d 07h	/t48/tags/rel_1_1/
19	enhance simulation result string	arniml	7413d 21h	/t48/tags/rel_1_1/
18	fix constant format	arniml	7413d 21h	/t48/tags/rel_1_1/
17	fix test	arniml	7413d 21h	/t48/tags/rel_1_1/
16	fix header	arniml	7413d 21h	/t48/tags/rel_1_1/
15	initial check-in	arniml	7414d 20h	/t48/tags/rel_1_1/
14	initial check-in	arniml	7414d 21h	/t48/tags/rel_1_1/
12	Imported sources	arniml	7414d 21h	/t48/tags/rel_1_1/
11	add description	arniml	7414d 22h	/t48/tags/rel_1_1/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7415d 20h	/t48/tags/rel_1_1/
9	initial check-in	arniml	7415d 20h	/t48/tags/rel_1_1/
8	initial check-in	arniml	7415d 22h	/t48/tags/rel_1_1/
7	initial check-in	arniml	7415d 22h	/t48/tags/rel_1_1/
6	moved to system directory	arniml	7415d 22h	/t48/tags/rel_1_1/
5	initial check-in	arniml	7416d 22h	/t48/tags/rel_1_1/
4	initial check-in	arniml	7416d 22h	/t48/tags/rel_1_1/