URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 51

Rev	Log message	Author	Age	Path
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7394d 14h	/t48/tags/rel_1_1/
49	Imported sources	arniml	7399d 16h	/t48/tags/rel_1_1/
48	update copyright notice	arniml	7399d 16h	/t48/tags/rel_1_1/
47	initial check-in	arniml	7399d 16h	/t48/tags/rel_1_1/
46	fix test	arniml	7401d 13h	/t48/tags/rel_1_1/
45	remove unused signals	arniml	7401d 13h	/t48/tags/rel_1_1/
44	default assignment for aux_carry_o	arniml	7401d 14h	/t48/tags/rel_1_1/
43	fix sensitivity list	arniml	7402d 15h	/t48/tags/rel_1_1/
42	change test values that match better to the test case	arniml	7402d 17h	/t48/tags/rel_1_1/
41	expand PATH	arniml	7402d 17h	/t48/tags/rel_1_1/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7402d 17h	/t48/tags/rel_1_1/
39	initial check-in	arniml	7404d 21h	/t48/tags/rel_1_1/
38	add measures to implement XCHD	arniml	7404d 21h	/t48/tags/rel_1_1/
37	add dump_compare support	arniml	7404d 21h	/t48/tags/rel_1_1/
36	make calculation of expected value more readable	arniml	7404d 22h	/t48/tags/rel_1_1/
35	initial check-in	arniml	7407d 15h	/t48/tags/rel_1_1/
34	fix test wrt AC	arniml	7410d 15h	/t48/tags/rel_1_1/
33	rename pX_limp to pX_low_imp	arniml	7410d 15h	/t48/tags/rel_1_1/
32	rename pX_limp to pX_low_imp	arniml	7410d 15h	/t48/tags/rel_1_1/
31	refer PROJECT_DIR variable	arniml	7410d 16h	/t48/tags/rel_1_1/