URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 95

Rev	Log message	Author	Age	Path
95	check counter inactivity	arniml	7386d 02h	/t48/tags/rel_1_1/
94	initial check-in	arniml	7386d 02h	/t48/tags/rel_1_1/
93	add support for line coverage evaluation with gcov	arniml	7386d 03h	/t48/tags/rel_1_1/
92	work around bug in Quartus II 4.0	arniml	7386d 03h	/t48/tags/rel_1_1/
91	fix edge detector bug for counter	arniml	7386d 03h	/t48/tags/rel_1_1/
90	intial check-in	arniml	7386d 03h	/t48/tags/rel_1_1/
89	initial check-in	arniml	7399d 23h	/t48/tags/rel_1_1/
88	allow memory bank switching during interrupts	arniml	7401d 01h	/t48/tags/rel_1_1/
87	abort gracfullt if memory bank switching does not work	arniml	7401d 01h	/t48/tags/rel_1_1/
86	update notice about expander port instructions	arniml	7401d 06h	/t48/tags/rel_1_1/
85	initial check-in	arniml	7401d 06h	/t48/tags/rel_1_1/
84	add if_timing module	arniml	7406d 21h	/t48/tags/rel_1_1/
83	connect if_timing to P2 output of T48	arniml	7406d 22h	/t48/tags/rel_1_1/
82	check expander timings	arniml	7406d 22h	/t48/tags/rel_1_1/
81	initial check-in	arniml	7407d 02h	/t48/tags/rel_1_1/
80	added if_timing	arniml	7407d 02h	/t48/tags/rel_1_1/
79	add if_timing module	arniml	7407d 02h	/t48/tags/rel_1_1/
78	adjust external timing of BUS	arniml	7407d 02h	/t48/tags/rel_1_1/
77	move from std_logic_arith to numeric_std	arniml	7407d 18h	/t48/tags/rel_1_1/
76	initial check-in	arniml	7407d 22h	/t48/tags/rel_1_1/