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[/] [t48/] [tags/] [rel_1_1/] [bench/] - Rev 234

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Rev Log message Author Age Path
234 cleanup & enhance external access arniml 6630d 02h /t48/tags/rel_1_1/bench/
233 added external ROM arniml 6630d 02h /t48/tags/rel_1_1/bench/
228 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom arniml 6631d 01h /t48/tags/rel_1_1/bench/
224 initial check-in arniml 6631d 01h /t48/tags/rel_1_1/bench/
220 new input xtal_en_i arniml 6632d 01h /t48/tags/rel_1_1/bench/
202 fix address assignment arniml 6862d 05h /t48/tags/rel_1_1/bench/
201 split low impedance markers for P2 arniml 6862d 05h /t48/tags/rel_1_1/bench/
200 add check for
tCP: Port Control Setup to PROG'
arniml 6862d 05h /t48/tags/rel_1_1/bench/
183 fix missing assignment to outclock arniml 6917d 09h /t48/tags/rel_1_1/bench/
160 add others to case statement arniml 7195d 06h /t48/tags/rel_1_1/bench/
140 remove tAW sanity check
conflicts with OUTL A, BUS
arniml 7234d 07h /t48/tags/rel_1_1/bench/
133 add checks for PSEN arniml 7278d 02h /t48/tags/rel_1_1/bench/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly
arniml 7391d 15h /t48/tags/rel_1_1/bench/
110 exchange syn_rom for lpm_rom arniml 7391d 15h /t48/tags/rel_1_1/bench/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data
arniml 7395d 12h /t48/tags/rel_1_1/bench/
83 connect if_timing to P2 output of T48 arniml 7417d 06h /t48/tags/rel_1_1/bench/
82 check expander timings arniml 7417d 06h /t48/tags/rel_1_1/bench/
81 initial check-in arniml 7417d 10h /t48/tags/rel_1_1/bench/
80 added if_timing arniml 7417d 10h /t48/tags/rel_1_1/bench/
68 connect T0 and T1 to P1 arniml 7424d 07h /t48/tags/rel_1_1/bench/

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