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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] - Rev 166

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Rev	Log message	Author	Age	Path
166	assign default for state_s	arniml	7030d 19h	/t48/tags/rel_1_1/rtl/vhdl/
165	add component wb_master.vhd	arniml	7031d 18h	/t48/tags/rel_1_1/rtl/vhdl/
164	initial check-in	arniml	7031d 18h	/t48/tags/rel_1_1/rtl/vhdl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7032d 17h	/t48/tags/rel_1_1/rtl/vhdl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7063d 21h	/t48/tags/rel_1_1/rtl/vhdl/
157	removed obsolete constant	arniml	7184d 18h	/t48/tags/rel_1_1/rtl/vhdl/
156	added hierarchy t8039_notri	arniml	7184d 18h	/t48/tags/rel_1_1/rtl/vhdl/
155	initial check-in	arniml	7184d 18h	/t48/tags/rel_1_1/rtl/vhdl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7185d 15h	/t48/tags/rel_1_1/rtl/vhdl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7186d 14h	/t48/tags/rel_1_1/rtl/vhdl/
149	update	arniml	7186d 14h	/t48/tags/rel_1_1/rtl/vhdl/
148	initial check-in	arniml	7186d 14h	/t48/tags/rel_1_1/rtl/vhdl/
145	remove PROG and end of XTAL2, see comment for details	arniml	7223d 17h	/t48/tags/rel_1_1/rtl/vhdl/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7223d 17h	/t48/tags/rel_1_1/rtl/vhdl/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7223d 18h	/t48/tags/rel_1_1/rtl/vhdl/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7223d 18h	/t48/tags/rel_1_1/rtl/vhdl/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7225d 04h	/t48/tags/rel_1_1/rtl/vhdl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7267d 13h	/t48/tags/rel_1_1/rtl/vhdl/
129	cleanup copyright notice	arniml	7329d 21h	/t48/tags/rel_1_1/rtl/vhdl/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7337d 00h	/t48/tags/rel_1_1/rtl/vhdl/

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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] - Rev 166

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