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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] - Rev 272

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Rev Log message Author Age Path
272 fix entity port names arniml 6461d 08h /t48/tags/rel_1_1/rtl/vhdl/
271 initial check-in arniml 6461d 08h /t48/tags/rel_1_1/rtl/vhdl/
270 fix component name arniml 6461d 09h /t48/tags/rel_1_1/rtl/vhdl/
262 name keyword added arniml 6596d 20h /t48/tags/rel_1_1/rtl/vhdl/
261 * name tag added
* restriction concerning expander port removed
arniml 6596d 20h /t48/tags/rel_1_1/rtl/vhdl/
249 Fix bug report
"Deassertion of PROG too early"
PROG is deasserted at end of XTAL3 now
arniml 6596d 20h /t48/tags/rel_1_1/rtl/vhdl/
247 initial check-in arniml 6596d 22h /t48/tags/rel_1_1/rtl/vhdl/
231 obsoleted by new memory concept arniml 6619d 20h /t48/tags/rel_1_1/rtl/vhdl/
227 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom arniml 6619d 20h /t48/tags/rel_1_1/rtl/vhdl/
226 replaced syn_ram with generic_ram_ena arniml 6619d 20h /t48/tags/rel_1_1/rtl/vhdl/
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6619d 20h /t48/tags/rel_1_1/rtl/vhdl/
224 initial check-in arniml 6619d 20h /t48/tags/rel_1_1/rtl/vhdl/
222 add note about clock enable for data memory RAM macro arniml 6620d 20h /t48/tags/rel_1_1/rtl/vhdl/
221 new input xtal_en_i arniml 6620d 20h /t48/tags/rel_1_1/rtl/vhdl/
220 new input xtal_en_i arniml 6620d 20h /t48/tags/rel_1_1/rtl/vhdl/
219 new input xtal_en_i gates xtal_i base clock arniml 6620d 20h /t48/tags/rel_1_1/rtl/vhdl/
216 assign clk_i to outclock arniml 6838d 00h /t48/tags/rel_1_1/rtl/vhdl/
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory
arniml 6838d 00h /t48/tags/rel_1_1/rtl/vhdl/
214 fix sensitivity list arniml 6845d 02h /t48/tags/rel_1_1/rtl/vhdl/
213 properly drive P1 and P2 with low impedance markers arniml 6849d 21h /t48/tags/rel_1_1/rtl/vhdl/

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