OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] [verif/] - Rev 265

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
265 tagging changed for io expander simulation arniml 6600d 08h /t48/tags/rel_1_1/sw/verif/
264 initial check-in arniml 6600d 08h /t48/tags/rel_1_1/sw/verif/
246 initial check-in arniml 6605d 07h /t48/tags/rel_1_1/sw/verif/
245 initial check-in arniml 6605d 07h /t48/tags/rel_1_1/sw/verif/
239 adapt t48 external ROM offset arniml 6623d 06h /t48/tags/rel_1_1/sw/verif/
238 initial check-in arniml 6623d 06h /t48/tags/rel_1_1/sw/verif/
237 initial check-in arniml 6623d 06h /t48/tags/rel_1_1/sw/verif/
236 initial check-in arniml 6623d 07h /t48/tags/rel_1_1/sw/verif/
229 rework hex/simulation targets arniml 6626d 05h /t48/tags/rel_1_1/sw/verif/
199 initial check-in arniml 6857d 09h /t48/tags/rel_1_1/sw/verif/
194 initial check-in arniml 6858d 20h /t48/tags/rel_1_1/sw/verif/
185 initial check-in arniml 6912d 09h /t48/tags/rel_1_1/sw/verif/
184 initial check-in arniml 6912d 10h /t48/tags/rel_1_1/sw/verif/
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"
arniml 7003d 11h /t48/tags/rel_1_1/sw/verif/
141 disable external memory to avoid conflicts with outl a, bus arniml 7229d 11h /t48/tags/rel_1_1/sw/verif/
131 update arniml 7273d 06h /t48/tags/rel_1_1/sw/verif/
130 initial check-in arniml 7273d 06h /t48/tags/rel_1_1/sw/verif/
125 exclude from dump compare arniml 7342d 18h /t48/tags/rel_1_1/sw/verif/
122 test MB after return from interrupt arniml 7343d 16h /t48/tags/rel_1_1/sw/verif/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7346d 09h /t48/tags/rel_1_1/sw/verif/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.