URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] - Rev 96

Rev	Log message	Author	Age	Path
96	select dedicated directorie(s) for regression	arniml	7390d 04h	/t48/tags/rel_1_2/
95	check counter inactivity	arniml	7390d 04h	/t48/tags/rel_1_2/
94	initial check-in	arniml	7390d 04h	/t48/tags/rel_1_2/
93	add support for line coverage evaluation with gcov	arniml	7390d 04h	/t48/tags/rel_1_2/
92	work around bug in Quartus II 4.0	arniml	7390d 04h	/t48/tags/rel_1_2/
91	fix edge detector bug for counter	arniml	7390d 04h	/t48/tags/rel_1_2/
90	intial check-in	arniml	7390d 04h	/t48/tags/rel_1_2/
89	initial check-in	arniml	7404d 01h	/t48/tags/rel_1_2/
88	allow memory bank switching during interrupts	arniml	7405d 03h	/t48/tags/rel_1_2/
87	abort gracfullt if memory bank switching does not work	arniml	7405d 03h	/t48/tags/rel_1_2/
86	update notice about expander port instructions	arniml	7405d 08h	/t48/tags/rel_1_2/
85	initial check-in	arniml	7405d 08h	/t48/tags/rel_1_2/
84	add if_timing module	arniml	7410d 23h	/t48/tags/rel_1_2/
83	connect if_timing to P2 output of T48	arniml	7410d 23h	/t48/tags/rel_1_2/
82	check expander timings	arniml	7410d 23h	/t48/tags/rel_1_2/
81	initial check-in	arniml	7411d 04h	/t48/tags/rel_1_2/
80	added if_timing	arniml	7411d 04h	/t48/tags/rel_1_2/
79	add if_timing module	arniml	7411d 04h	/t48/tags/rel_1_2/
78	adjust external timing of BUS	arniml	7411d 04h	/t48/tags/rel_1_2/
77	move from std_logic_arith to numeric_std	arniml	7411d 20h	/t48/tags/rel_1_2/