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[/] [t48/] [tags/] [rel_1_2/] [bench/] [vhdl/] - Rev 233

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Rev Log message Author Age Path
233 added external ROM arniml 6623d 03h /t48/tags/rel_1_2/bench/vhdl/
228 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom arniml 6624d 03h /t48/tags/rel_1_2/bench/vhdl/
224 initial check-in arniml 6624d 03h /t48/tags/rel_1_2/bench/vhdl/
220 new input xtal_en_i arniml 6625d 03h /t48/tags/rel_1_2/bench/vhdl/
202 fix address assignment arniml 6855d 06h /t48/tags/rel_1_2/bench/vhdl/
201 split low impedance markers for P2 arniml 6855d 06h /t48/tags/rel_1_2/bench/vhdl/
200 add check for
tCP: Port Control Setup to PROG'
arniml 6855d 06h /t48/tags/rel_1_2/bench/vhdl/
183 fix missing assignment to outclock arniml 6910d 10h /t48/tags/rel_1_2/bench/vhdl/
160 add others to case statement arniml 7188d 08h /t48/tags/rel_1_2/bench/vhdl/
140 remove tAW sanity check
conflicts with OUTL A, BUS
arniml 7227d 08h /t48/tags/rel_1_2/bench/vhdl/
133 add checks for PSEN arniml 7271d 03h /t48/tags/rel_1_2/bench/vhdl/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly
arniml 7384d 16h /t48/tags/rel_1_2/bench/vhdl/
110 exchange syn_rom for lpm_rom arniml 7384d 16h /t48/tags/rel_1_2/bench/vhdl/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data
arniml 7388d 13h /t48/tags/rel_1_2/bench/vhdl/
83 connect if_timing to P2 output of T48 arniml 7410d 07h /t48/tags/rel_1_2/bench/vhdl/
82 check expander timings arniml 7410d 07h /t48/tags/rel_1_2/bench/vhdl/
81 initial check-in arniml 7410d 11h /t48/tags/rel_1_2/bench/vhdl/
80 added if_timing arniml 7410d 11h /t48/tags/rel_1_2/bench/vhdl/
68 connect T0 and T1 to P1 arniml 7417d 09h /t48/tags/rel_1_2/bench/vhdl/
67 initial check-in arniml 7417d 09h /t48/tags/rel_1_2/bench/vhdl/

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