URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] [sw/] [verif/] - Rev 131

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Rev	Log message	Author	Age	Path
131	update	arniml	7266d 20h	/t48/tags/rel_1_2/sw/verif/
130	initial check-in	arniml	7266d 20h	/t48/tags/rel_1_2/sw/verif/
125	exclude from dump compare	arniml	7336d 09h	/t48/tags/rel_1_2/sw/verif/
122	test MB after return from interrupt	arniml	7337d 06h	/t48/tags/rel_1_2/sw/verif/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7340d 00h	/t48/tags/rel_1_2/sw/verif/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7380d 09h	/t48/tags/rel_1_2/sw/verif/
102	update for changes in address space of external memory	arniml	7384d 06h	/t48/tags/rel_1_2/sw/verif/
99	initial check-in	arniml	7384d 06h	/t48/tags/rel_1_2/sw/verif/
97	initial check-in	arniml	7384d 07h	/t48/tags/rel_1_2/sw/verif/
95	check counter inactivity	arniml	7385d 04h	/t48/tags/rel_1_2/sw/verif/
94	initial check-in	arniml	7385d 05h	/t48/tags/rel_1_2/sw/verif/
90	intial check-in	arniml	7385d 05h	/t48/tags/rel_1_2/sw/verif/
89	initial check-in	arniml	7399d 02h	/t48/tags/rel_1_2/sw/verif/
87	abort gracfullt if memory bank switching does not work	arniml	7400d 04h	/t48/tags/rel_1_2/sw/verif/
85	initial check-in	arniml	7400d 09h	/t48/tags/rel_1_2/sw/verif/
57	abort if no interrupt occurs	arniml	7415d 23h	/t48/tags/rel_1_2/sw/verif/
46	fix test	arniml	7423d 23h	/t48/tags/rel_1_2/sw/verif/
42	change test values that match better to the test case	arniml	7425d 03h	/t48/tags/rel_1_2/sw/verif/
39	initial check-in	arniml	7427d 07h	/t48/tags/rel_1_2/sw/verif/
36	make calculation of expected value more readable	arniml	7427d 07h	/t48/tags/rel_1_2/sw/verif/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] [sw/] [verif/] - Rev 131

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