URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] [sw/] [verif/] - Rev 239

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Rev	Log message	Author	Age	Path
239	adapt t48 external ROM offset	arniml	6653d 11h	/t48/tags/rel_1_2/sw/verif/
238	initial check-in	arniml	6653d 11h	/t48/tags/rel_1_2/sw/verif/
237	initial check-in	arniml	6653d 11h	/t48/tags/rel_1_2/sw/verif/
236	initial check-in	arniml	6653d 12h	/t48/tags/rel_1_2/sw/verif/
229	rework hex/simulation targets	arniml	6656d 10h	/t48/tags/rel_1_2/sw/verif/
199	initial check-in	arniml	6887d 14h	/t48/tags/rel_1_2/sw/verif/
194	initial check-in	arniml	6889d 01h	/t48/tags/rel_1_2/sw/verif/
185	initial check-in	arniml	6942d 14h	/t48/tags/rel_1_2/sw/verif/
184	initial check-in	arniml	6942d 15h	/t48/tags/rel_1_2/sw/verif/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7033d 16h	/t48/tags/rel_1_2/sw/verif/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7259d 16h	/t48/tags/rel_1_2/sw/verif/
131	update	arniml	7303d 11h	/t48/tags/rel_1_2/sw/verif/
130	initial check-in	arniml	7303d 11h	/t48/tags/rel_1_2/sw/verif/
125	exclude from dump compare	arniml	7372d 23h	/t48/tags/rel_1_2/sw/verif/
122	test MB after return from interrupt	arniml	7373d 21h	/t48/tags/rel_1_2/sw/verif/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7376d 14h	/t48/tags/rel_1_2/sw/verif/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7417d 00h	/t48/tags/rel_1_2/sw/verif/
102	update for changes in address space of external memory	arniml	7420d 21h	/t48/tags/rel_1_2/sw/verif/
99	initial check-in	arniml	7420d 21h	/t48/tags/rel_1_2/sw/verif/
97	initial check-in	arniml	7420d 22h	/t48/tags/rel_1_2/sw/verif/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] [sw/] [verif/] - Rev 239

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